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november 2010 ? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 FAN5234 ? dual mobile-friendly pwm / pfm controller FAN5234 dual mobile-friendly pwm / pfm controller features ? wide input voltage range for mobile systems: 2v to 24v ? excellent dynamic response with voltage feed- forward and average-current-mode control ? lossless current sensing on low-side mosfet or precision over-current via sense resistor ? v cc under-voltage lockout ? power-good signal ? light-load hysteretic mode maximizes efficiency ? 300khz or 600khz operation ? tssop16 package applications ? mobile pc regulator ? handheld pc power related resources ? application note ? an-6002 component calculations and simulation tools for FAN5234 or fan5236 ? application note ? an-1029 maximum power enhancement techniques for so-8 power mosfet description the FAN5234 pwm controller provides high efficiency and regulation with an adjustable output from 0.9v to 5.5v required to power i/o, chip-sets, memory banks, or peripherals in high-perform ance notebook computers, pdas, and internet appliances. synchronous rectification and hysteretic operation at light loads contribute to a high efficiency over a wide range of loads. the hysteretic mode of operation can be disabled if pwm mode is desired for all load levels. efficiency is further enhanced by using the mosfet?s r ds(on) as a current-sense component. feed-forward ramp modulation, average current mode control, and internal feedback compensation provide fast response to load transients. the FAN5234 monitors these outputs and generates a pgood (pow er-good) signal when the soft-start is completed and the output is within 10% of its set point. a built-in over-voltage protection prevents the output voltage from going above 120% of the set point. normal operation is automatically restored when the over-voltage conditions cease. under-voltage protection latches the chip off when the output drops below 75% of its set value after the soft- start sequence is completed. an adjustable over-current function monitors the output current by sensing the voltage drop across the lower mosfet. ordering information part number operating temperature range package packing method FAN5234mtcx -10 to +85c 16-lead, thin-shrink sma ll-outline package (tssop) tape and reel
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 2 FAN5234 ? dual mobile-friendly pwm / pfm controller typical application sw fa n5 234 10 c6 l1 q1b 14 ilim 1 4 r1 r2 11 vcc +5 d1 +5 15 13 r3 12 c4 8 r5 pgood 2 +5 9 isns pgnd q1a 6 vsen ldrv hdrv bo ot vin c5 c1 1.8v at 3.5a r4 vin (b a tter y ) = 2 to 24v c2 agnd en 3 ss1 7 c3 16 fpwm vout 5 figure 1. 1.18v output regulator block diagram figure 2. block diagram
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 3 FAN5234 ? dual mobile-friendly pwm / pfm controller pin configuration vin pgood en ilim vout vsen ss agnd fa n5 23 4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 fpwm boot hdrv sw isns vcc ldrv pgnd figure 3. pin configuration pin definitions pin # name description 1 vin input voltage . connect to main input power source (battery), also used to program operating frequency for low input voltage operation (see table 1). 2 pgood power-good flag . an open-drain output that pulls low when v sen is outside of a 10% range of the 0.9v reference. 3 en enable . enables operation when pulled to logic high. toggling en resets the regulator after a latched fault condition. this is a cmos input whose state is indeterminate if left open. 4 ilim current limit . a resistor from this pin to gnd sets the current limit. 5 vout output voltage . connect to output voltage. used for regulation to ensure a smooth transition during mode changes. when v out is expected to exceed v cc , tie this pin to v cc . 6 vsen output voltage sense . the feedback from the output. used for regulation as well as power-good, under-voltage, and over-voltage protection monitoring. 7 ss soft-start . a capacitor from this pin to gnd program s the slew rate of the converter during initialization, when this pin is charged with a 5a current source. 8 agnd analog ground . this is the signal ground reference for the ic. all voltage levels are measured with respect to this pin. 9 pgnd power ground . the return for the low-side mosfet driver output. connect to the gate of the low-side mosfet. 10 ldrv low-side drive . the low-side (lower) mosfet driver output. connect to the gate of the low-side mosfet. 11 vcc supply voltage . this pin powers the chip as well as the ldrv buffers. the ic starts to operate when voltage on this pin exceeds 4.6v (uvlo rising) and shuts down when it drops below 4.3v (uvlo falling). 12 isns current-sense input . monitors the voltage drop across the lower mosfet or external sense resistor for current feedback. 13 sw switching node . return for the high-side mosfet driver and a current-sense input. connect to source of high-side mosfet and low-side mosfet drain. 14 hdrv high-side drive . high-side (upper) mosfet driver output. connect to the gate of the high- side mosfet. 15 boot boot . positive supply for the upper mosfet driver. connect as shown in figure 2. 16 fpwm forced pwm mode . when logic high, inhibits the r egulation from entering hysteretic mode.
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 4 FAN5234 ? dual mobile-friendly pwm / pfm controller absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc v cc supply voltage 6.5 v v in v in supply voltage 27 v boot, sw, isns, hdrv pins 33 v boot to sw pins 6.5 v all other pins -0.3 v cc +0.3 v t j junction temperature -10 +150 oc t stg storage temperature -65 +150 oc t l lead soldering temperature, 10 seconds +300 oc recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit v cc v cc supply voltage 4.75 5.00 5.25 v v in v in supply voltage 24 v t a ambient temperature -10 +85 c ja thermal resistance, junction to ambient 112 c/w
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 5 FAN5234 ? dual mobile-friendly pwm / pfm controller electrical characteristics recommended operating conditions, unless otherwise noted. symbol parameter conditions min. typ. max. units power supplies i vcc v cc current ldrv, hdrv open; v sen forced above regulation point 850 1300 a shutdown (en-0) 5 15 a i sink v in current, sinking vin pin = input voltage source 10 20 30 a i source v in current, sourcing vin pin = gnd 7 15 20 a i sd v in current, shutdown 1 a v uvlo uvlo threshold rising v cc 4.30 4.55 4.75 v falling 4.10 4.27 4.50 v uvloh uvlo hysteresis 0.1 0.5 v oscillator f osc frequency v in > 5v 255 300 345 khz v in = 0v 510 600 690 v pp ramp amplitude v in = 16v 2 v v in > 5v 1.25 v ramp ramp offset 0.5 v g ramp / v in gain v in 3v 125 mv/v 1v < v in < 3v 250 reference and soft-start v ref internal reference voltage 0.891 0.900 0.909 v i ss soft-start current at startup 5 a v ss soft-start complete threshold 1.5 v pwm converter load regulation i out from 0 to 3a, v in from 2 to 24v -1 +1 % i sen v sen bias current 50 80 150 na vout pin input impedance 40 55 65 k uvlo tsd under-voltage shutdown % of set point, 2s noise filter 70 75 80 % i sns over-current threshold r ilim = 68.5k , figure 6 115 144 172 % uvlo over-voltage threshold % of set point, 2s noise filter 113 120 a output drivers hdrv output resistance sourcing 8.0 15.0 sinking 3.2 4.0 ldrv output resistance sourcing 8.0 15.0 sinking 1.5 2.4 continued on following page?
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 6 FAN5234 ? dual mobile-friendly pwm / pfm controller electrical characteristics (continued) symbol parameter conditions min. typ. max. units power-good output and control pins lower threshold % of set point, 2s noise filter 86 92 % upper threshold % of set point, 2s noise filter 110 115 % pgood output low i pgood = 4ma 0.5 v leakage current v pullup = 5v 1 a soft-start vo ltage, pgood enabled 1.5 % v ref2 en, fpwm inputs v inh input high 2 v v inl input low 0.8 v
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 7 FAN5234 ? dual mobile-friendly pwm / pfm controller functional description overview the FAN5234 is a pwm controller intended for low- voltage power applications in notebook, desktop, and sub-notebook pcs. the output voltage of the controller can be set in the range of 0.9v to 5.5v by an external resistor divider. the synchronous buck converter can operate from an unregulated dc source (such as a notebook battery), with voltage ranging from 2v to 24v, or from a regulated system rail. in either case, the ic is biased from a +5v source. the pwm modulator uses an average-current- mode control with input voltage feed-forward for simplified feedback loop compensation and improved line regulation. the controller includes integrated feedback loop compensation that dramatically reduces the number of external components. depending on the load level, the converter can operate in fixed-frequency pwm mode or in hysteretic mode. switch-over from pwm to hysteretic mode improves the converters' efficiency at light loads and prolongs battery run time. in hysteretic mode, a comparator is synchronized to the main clock to allow seamless transition between the operational modes and reduced channel-to-channel interaction. the hysteretic mode of operation can be inhibited independently using the fpwm pin if variable frequency operation is not desired. oscillator table 1. converter operating modes mode f sw converter power vin pin battery 300 2 to 24v battery (>5v) fixed 300 300 <5.5v fixed 100k to gnd fixed 600 600 <5.5v fixed gnd when v in is from the battery, the oscillator ramp amplitude is proportional to v in , providing voltage feed- forward control for improved loop response. when in either of the fixed modes, oscillator ramp amplitude is fixed. the operating frequency is determined according to the connection on the vin pin (see table 1) . initialization and soft start assuming en is high, FAN5234 is initialized when v cc exceeds the rising uvlo threshold. should v cc drop below the uvlo threshold, an internal power-on reset function disables the chip. the voltage at the positive input of the error amplifier is limited by the voltage at the ss pin, which is charged with 5ma current source. once c ss has charged to v ref (0.9v), the output voltage is in regulation. the time it takes ss to reach 0.9v is: 5 xc 9 . 0 t ss 9 . 0 = (1) where t 0.9 is in seconds if c ss is in f. when ss reaches 1.5v, the power-good outputs are enabled and hysteretic mode is allowed. the converter is forced into pwm mode during soft-start. operation mode control the mode-control circuit changes the converter?s mode from pwm to hysteretic and vice versa based on the voltage polarity of the sw node when the lower mosfet is conducting and just before the upper mosfet turns on. for continuous inductor current, the sw node is negative when the lower mosfet is conducting and the converters operate in fixed- frequency pwm mode, as shown in figure 4. this mode achieves high efficiency at nominal load. when the load current decreases to the point where the inductor current flows through the lower mosfet in the ?reverse? direction, the sw node becomes positive and the mode is changed to hysteretic, which achieves higher efficiency at low currents by decreasing the effective switching frequency. to prevent accidental mode change or "mode chatter," the transition from pwm to hysteretic mode occurs when the sw node is positive for eight consecutive clock cycles ( see figure 4 ). the polarity of the sw node is sampled at the end of the lower mosfet conduction time. at the transition between pwm and hysteretic mode, both the upper and lower mosfets are turned off. the sw node ?rings? based on the output inductor and the parasitic capacitance on the sw node and settles out at the value of the output voltage. the boundary value of inductor current, where current becomes discontinuous, is estimated by the following: ? ? ? ? ? ? ? ? ? ? ? = in out sw out out in ) dis ( load v l f 2 v ) v v ( i (2) hysteretic mode conversely, the transition from hysteretic mode to pwm mode occurs when the sw node is negative for eight consecutive cycles. a sudden increase in the output current causes a change from hysteretic to pwm mode. this load increase causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor esr. if the load causes the output voltage (as presented at v sen ) to drop below the hysteretic regulation level (20mv below v ref ), the mode is changed to pwm on the next clock cycle. in hysteretic mode, the pwm comparator and the error amplifier that provide control in pwm mode are inhibited and the hysteretic comparator is activated. in hysteretic mode the low-side mosfet is operated as a synchronous rectifier, where the voltage across (v ds(on) ) is monitored and it is switched off when v ds(on) goes positive (current flowing back from the load), allowing the diode to block reverse conduction.
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 8 FAN5234 ? dual mobile-friendly pwm / pfm controller pwm mo d e hyst eret i c mod e hyst eret i c mod e pwm mo d e 12345678 v core i l 0 v core i l 0 1 23 4 56 7 8 figure 4. transitioning between pwm and hysteretic mode the hysteretic comparator causes hdrv turn-on when the output voltage (at v sen ) falls below the lower threshold (10mv below v ref ) and terminates the pfm signal when v sen rises over the higher threshold (5mv above v ref ). the switching frequency is primarily a function of: ? spread between the two hysteretic thresholds ? i load ? output inductor and capacitor esr a transition back to pwm continuous conduction mode or (ccm) occurs when the inductor current rises sufficiently to stay positive for eight consecutive cycles. this occurs when: ? ? ? ? ? ? = esr 2 v i hysteresis ) ccm ( load (3) where v hysteresis = 15mv and esr is the equivalent series resistance of c out . due to different control mechanisms, the value of the load current where transition into pwm operation takes place is typically higher compared to the load level at which transition into hysteretic mode occurs. hysteretic mode can be disabled by setting the fpwm pin high. current processing the following discussion refers to figure 6. the current through r sense resistor (i sns ) is sampled shortly after q2 is turned on. that current is held and summed with the output of the error amplifier. this effectively creates a current-mode control loop. the resistor connected to the isns pin (r sense ) sets the gain in the current feedback loop. equation 4 estimates the recommended value of r sense as a function of the maximum load current (i load(max) ) and the value of the mosfet r ds(on) . r sense must be kept higher than 700 even if the number calculated comes out less than 700 : ? ? ? ? ? ? ? ? ? = 100 a 150 r i r ) on ( ds ) max ( load sense (4) setting the current limit a ratio of i sns is also compared to the current established when a 0.9v internal reference drives the ilim pin: ? ? ? ? ? ? ? ? ? ? + = ) on ( ds sense load lim r ) r 100 ( x i 11 r (5) since the tolerance on the current limit is largely dependent on the ratio of the external resistors, it is fairly accurate if the voltage drop on the switching node side of r sense is an accurate representation of the load current. when using the mosfet as the sensing element, the variation of r ds(on) causes proportional variation in i sns . this value varies from device to device and has a typical junction temperature coefficient of about 0.4%/c (consult the mosfet datasheet for actual values) , the actual current limit set point decreases proportional to increasing mosfet die temperature. a factor of 1.6 in the current limit set point should compensate for all mosfet r ds(on) variations, assuming the mosfet?s heat sinking keep its operating die temperature below 125c. ldrv pgnd isns r sense r1 q2 figure 5. improving current-sensing accuracy
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 9 FAN5234 ? dual mobile-friendly pwm / pfm controller ldrv pgnd isns in+ in- 2.5v ilim det. r sense ss 1.5m c ss vsen vtoi reference and soft-start 17pf i2 = ilim * 11 ilim 0.9v r ili m ilim s/h to pwm comp 300k 0.17pf 4.14k isns isns figure 6. current limit / summing circuits more accurate sensing can be achieved by using a resistor (r1) instead of the r ds(on) of the fet, as shown in figure 5. this approach causes higher losses, but yields greater accuracy in both v droop and i limit . r1 is a low value (e.g. 10m ) resistor. current limit (i limit ) should be set high enough to allow inductor current to rise in response to an output load transient. typically, a factor of 1.2 is sufficient. since i limit is a peak current cut-off value, multiply i load(max) by the inductor ripple current (use 25%). for example, in figure 1 the target for i limit would be: i limit > 1.2 x 1.25 x 1.6 x 3.5a 8.5a (6) duty cycle clamp during severe load increase, the error amplifier output can go to its upper limit, pushing a duty cycle to almost 100% for a significant amount of time. this could cause a large increase of the inductor current and lead to a long recovery from a transient over-current condition or even to a failure at high input voltages. to prevent this, the output of the error amplifier is clamped to a fixed value after two clock cycles if severe output voltage excursion is detected, limiting maximum duty cycle to: ? ? ? ? ? ? ? ? + = in v 4 . 2 v v dc in out max (7) this is designed to not interfere with normal pwm operation. when fpwm is grounded, the duty cycle clamp is disabled and the maximum duty cycle is 87%. gate driver the adaptive gate control logic translates the internal pwm control signal into the mosfet gate drive signals, providing necessary amplification, level shifting, and shoot-through protection. it also has functions that help optimize the ic performance over a wide range of operating conditions. since mosfet switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower mosfets. the lower mosfet drive is not turned on until t he gate-to-source voltage of the upper mosfet has decreased to less than approximately 1v. similarly, the upper mosfet is not turned on until the gate-to-source voltage of the lower mosfet has decreased to less than approximately 1v. this allows a wide variety of upper and lower mosfets to be used without concern for simultaneous conduction or shoot-through. there must be a low-resistance, low-inductance path between the driver pin and the mosfet gate for the adaptive dead-time circuit to work properly. any delay along that path subtracts from the delay generated by the adaptive dead-time circuit and shoot-through may occur. frequency loop compensation due to the implemented current-mode control, the modulator has a single-pole response with -1 slope at frequency determined by load. therefore: o o c r 2 1 f po = (8) where r o is load resistance and c o is load capacitance. for this type of modulator, type-2 compensation circuit is usually sufficient. to reduce the number of external components and simplify the design task, the pwm controller has an internally compensated error amplifier. figure 7 shows a type two amplifier, its response, and the responses of a current mode modulator and the converter. the type-2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole.
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 10 FAN5234 ? dual mobile-friendly pwm / pfm controller c o n v e r t e r 0 14 18 modulator f p0 f z f p e r r o r a m p . r1 r2 ea out c1 c2 ref v in figure 7. compensation khz 6 c r 2 1 f 1 2 z = = (9) khz 600 2 c r 2 1 f 2 p = = (10) this region is also associated with phase ?bump? or reduced phase shift. the amount of phase shift reduction depends the width of the region of flat gain and has a maximum value of 90. to further simplify the converter compensation, t he modulator gain is kept independent of the input voltage variation by providing feed-forward of v in to the oscillator ramp. the zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. the crossover frequency appears at the point where the modulator attenuation equals the amplifier high-frequency gain. the system designer must specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. with this type of compensation, plenty of phase margin is achieved due to zero-pole pair phase ?boost.? conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. in this case, the esr zero placed within the 10khz to 50khz range gives some additional phase boost. there is an opposite trend in mobile applications to keep the output capacitor as small as possible. protections the converter output is monitored and protected against extreme overload, short circuit, over-voltage, and under-voltage conditions. a sustained overload on an out put sets t he pgood pin low and latches off the chip. operation is restored by cycling the v cc voltage or by toggling the en pin. if v out drops below the under-voltage threshold, the chip shuts down immediately. over-current sensing if the circuit's current-limit signal (?i lim det? in figure 6) is high at the beginning of a clock cycle, a pulse- skipping circuit is activated and hdrv is inhi bited. the circuit continues to pulse skip in this manner for the next eight clock cycles. if at any time from the ninth to the sixteenth clock cycle, the i lim det is again reached, the over-current protection latch is set, disabling the chip. if i lim det does not occur between cycles 9 and 16, normal operation is restored and the over-current circuit resets itself. 1 2 3 ch1 5.0v ch3 2.0aw ch2 100mv m 10.0s i l pgood 8 clk v out figure 8. over-current protection waveforms over-voltage / under-voltage protection should the v sen voltage exceed 120% of v ref (0.9v) due to an upper mosfet failure or for other reasons, the over-voltage protection comparator forces ldrv high. this action actively pulls down the output voltage and, in the event of the upper mosfet failure, eventually blows the battery fuse. as soon as the output voltage drops below the threshold, the ovp comparator is disengaged. this ovp scheme provides a ?soft? crowbar function to tackle severe load transients and does not invert the output voltage when activated ? a common problem for latched ovp schemes. similarly, if an output short-circuit or severe load transient causes the output to droop to less than 75% of its regulation set point, the regulator shuts down. over-temperature protection the chip incorporates an ov er-temperature protection circuit that shuts the chip down when a die temperature reaches 150c. normal operation is restored at die temperature below 125c with internal power on reset asserted, resulting in a full soft-start cycle.
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 11 FAN5234 ? dual mobile-friendly pwm / pfm controller design and component selection guidelines as an initial step, define operating input voltage range, output voltage, and minimum and maximum load currents for the controller. for the examples in the following discussion, select components for: v in from 5v to 20v v out = 1.8v at i load(max) = 3.5a setting the output voltage the internal reference is 0.9v. the output is divided down by a voltage divider to the vsen pin (for example, r1 and r2 in figure 1). the output voltage therefore is: 1 r v 9 . 0 v 2 r v 9 . 0 out ? = (11) to minimize noise pickup on this node, keep the resistor to gnd (r2) below 2k; for example r2 at 1.82k, then choose r5: ( ) ( ) k 82 . 1 9 . 0 9 . 0 v 8 . 1 k 82 . 1 5 r = ? = (12) output inductor selection the minimum practical output inductor value keeps inductor current just on the boundary of continuous conduction at some minimum load. the industry standard practice is to choose the ripple current to be somewhere from 15% to 35% of the nominal current. at light-load, the ripple current determines the point where the converter automatically switches to hysteretic mode to sustain high efficiency. the following equations help to choose the proper value of the output filter inductor: esr v 1 2 i out min ? = = (13) where i is the inductor ripple current, which is chosen for 20% of the full load current and v out is the maximum output ripple voltage allowed: in out sw out in v v i f v v l ? = (14) for this example, use: v in = 20v, v out = 1.8v ? i = 20% x 3.5a = 0.7a f sw = 300khz. (15) therefore; l ? 8h (16) output capacitor selection the output capacitor serves two major functions in a switching power supply. along with the inductor, it filters the sequence of pulses produced by the switcher and it supplies the load transient currents. the output capacitor requirements are usually dictated by esr, inductor ripple current ( i), and the allowable ripple voltage ( v): i v esr < (17) for this example, = = = m 142 a 7 . 0 v 1 . 0 i v esr ) max ( in addition, the capacitor's esr must be low enough to allow the converter to stay in regulation during a load step. the ripple voltage due to esr for the converter in figure 1 is 100mv pp . some additional ripple will appear due to the capacitance value itself: sw out f 8 c i v = (18) which is only about 1.5mv for the converter in figure 1 and can be ignored. the capacitor must also be rated to withstand the rms current, which is approximately 0.3 x ( i) or about 210ma for the converter in figure 1. high-frequency decoupling capacitors should be placed as close to the loads as physically possible. input capacitor selection the input capacitor should be selected by its ripple current rating. the input rms current at maximum load current (i l ) is: 2 l rms d d i i ? = (19) where the converter duty cycle; in out v v d = , which for the circuit in figure 1, with v in =6, calculates to a 6 . 1 i rms = . power mosfet selection losses in a mosfet are the sum of its switching (p sw ) and conduction (p cond ) losses. in typical applications, the FAN5234 converter's output voltage is low with respect to its input voltage. therefore, the lower mosfet (q2) is conducting the full-load current for most of the cycle. q2 should therefore be selected to minimize conduction losses, thereby selecting a mosfet with low r ds(on) . in contrast, the high-side mo sfet (q1) has a shorter duty cycle, and its conduction loss has less impact. q1, however, sees most of the switching losses, so q1's primary selection criter ia should be gate charge.
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 12 FAN5234 ? dual mobile-friendly pwm / pfm controller high-side losses figure 9 shows a mosfet's switching interval, with the upper graph being the voltage and current on the drain- to-source and the lower graph detailing v gs vs. time with a constant current charging the gate. the x-axis therefore is also representative of gate charge (q g ). c iss = c gd + c gs , and it controls t1, t2, and t4 timing. c gd receives the current from the gate driver during t3 (as v ds is falling). the gate charge (q g ) parameters on the lower graph are either specified or can be derived from mosfet datasheets. assuming switching losses are about the same for both the rising edge and falling edge, q1's switching losses, occur during the shaded time when the mosfet has voltage across it and current through it. these losses are given by: p upper = p sw + p cond (20) where: sw l ds sw f t 2 2 i v p s ? ? ? ? ? ? ? ? = (21) ) on ( ds out out cond r i v v p 2 in ? ? ? ? ? ? ? ? = (22) p upper is the upper mosfet's total losses and p sw and p cond are the switching and conduction losses for a given mosfet. r ds(on) is at the maximum junction temperature (t j ). t s is the switching period (rise or fall time) and is t2+t3 in figure 9. v sp t1 t2 t3 4.5v t4 t5 q g(sw) v ds i d q gs q gd v th v gs c iss c gd c iss figure 9. switching losses and q g (c iss = c gs || c gd ) c gd r d r gate c gs hdrv 5v sw v in g figure 10. drive equivalent circuit the driver?s impedance and c iss determine t2 while t3?s period is controlled by the driver's impedance and q gd . since most of t s occurs when v gs = v sp , use a constant current assumption for the driver to simplify the calculation of t s : ? ? ? ? ? ? ? ? + ? = = gate driver sp cc ) sw ( g driver ) sw ( g r r v v q i q t s (23) most mosfet vendors specify q gd and q gs . q g(sw) can be determined as: q g(sw) = q gd + q gs ? q th (24) where q th is the gate charge required to get the mosfet to its threshold (v th ). for the high-side mosfet, v ds = v in , which can be as high as 20v in a typical portable application. care should be taken to include the delivery of the mosfet's gate power (p gate ) in calculating the power dissipation required for the FAN5234: sw cc g ate g f v q p = (25) where q g is the total gate charge to reach v cc . low-side losses q2 switches on or off with its parallel schottky diode conducting; therefore, v ds ? 0.5v. since p sw is proportional to v ds , q2's switching losses are negligible and q2 is selected based on r ds(on) only. conduction losses for q2 are given by: ( ) ) on ( ds out cond r i d 1 p 2 ? = (26) where r ds(on) is the r ds(on) of the mosfet at the highest operating junction temperature and in out v v d = is the minimum duty cycle for the converter. since d min <20% for portable computers, (1-d) 1 produces a conservative result, simplifying the calculation. the maximum power dissipation (p d(max) ) is a function of the maximum allowable die temperature of the low- side mosfet, the ja , and the maximum allowable ambient temperature rise: ja ) max ( a ) max ( j ) max ( d t t p ? = (27) ja depends primarily on the amount of pcb area that can be devoted to heat sinking (see an-1029 ? maximum power enhancement techniques for so-8 power mosfet for mosfet thermal information) .
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 13 FAN5234 ? dual mobile-friendly pwm / pfm controller table 2. build of materials for 1.8v, 3.5a regulator description qty. ref. vendor part number capacitor 68 f, tantalum, 25v, esr 95m 1 c1 avx. tpsv686*025#095 capacitor 10nf, ceramic 2 c2, c3 any capacitor 68 f, tantalum, 6v, esr 1.8 1 c4 avx. tajv686*006 capacitor 0.1 f, ceramic 2 c5 any capacitor 330 f, tantalum, 6v, esr 100m 2 c6 avx. tpse337*006#0100 1.82k , 1% resistor 2 r1, r2 any 1.3k , 1% resistor 1 r3 any 100k , 5% resistor 1 r4 any 56.2k , 1% resistor 1 r5 any schottky diode; 0.5a, 20v 2 d1 fairchild semiconductor mbr05s0l inductor 8.4 h, 6a 1 l1 any dual mosfet with schottky 1 q fairchild semiconductor fds6986as (1) pwm controller 1 u1 fairchild semiconductor FAN5234 note: 1. if currents above 4a continuous are required, use single so-8 packages. for more information, refer to the power mosfet selection section and an-6002 for design calculations. layout considerations switching converters, even during normal operation, produce short pulses of current that could cause substantial ringing and be a source of emi if layout constrains are not observed. there are two sets of critical components in a dc-dc converter. the switching power components process large amounts of energy at high rate and are noise generators. the low-power components responsible for bias and feedback functions are sensitive to noise. a multi-layer printed circuit board is recommended. dedicate one solid layer for a ground plane. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. notice all the nodes that are subjected to high dv/dt voltage swing; such as sw, hdrv, and ldrv. all surrounding circuitry tends to couple the signals from these nodes through stray capacitance. do not oversize copper traces connected to these nodes. do not place traces connected to the feedback components adjacent to these traces. it is not recommended to use high density interconnect systems, or micro-vias, on these signals. the use of blind or buried vias should be limited to the low-current signals only. the use of normal thermal vias is at the discretion of the designer. keep the wiring traces from the ic to the mosfet gate and source as short as possible and capable of handling peak currents of 2a. minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. locate small critical com ponents, like the soft-start capacitor and current sense resistors, as close as possible to the respective pins of the ic. the FAN5234 utilizes advanced packaging technologies with lead pitches of 0.6mm. high- performance analog semiconductors utilizing narrow lead spacing may require s pecial considerations in pwb design and manufacturing. it is critical to maintain proper cleanliness of the area surrounding these devices. it is not recommended to use any type of rosin or acid core solder, or the use of flux, in either the manufacturing or touch up process as these may contribute to corrosion or enable electro-migration and / or eddy currents near the sensitive low-current signals. when chemicals are used on or near the pwb, it is suggested that the entire pwb be cleaned and dried completely before applying power.
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 14 FAN5234 ? dual mobile-friendly pwm / pfm controller physical dimensions 0.65 4.40.1 mtc16rev4 0.11 4.55 5.00 5.000.10 12 7.35 4.45 1.45 5.90 figure 11. 16-lead, thin-shrink outline package package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
? 2004 fairchild semiconductor corporation www.fairchildsemi.com FAN5234 ? rev. 2.0.0 15 FAN5234 ? dual mobile-friendly pwm / pfm controller

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